Engine category

Embedded, Digital, and Interfaces

Published tools in this category solve distinct design decisions. Each keeps its assumptions, limits, and next decision visible.

Exact relationship

I2C pullup resistor designer

Calculate the feasible I2C pullup-resistance interval from supply voltage, low-level sink limits, bus capacitance, and rise-time limit.

Exact ideal relationship

Digital logic-level compatibility

Calculate high and low noise margins between a driver's guaranteed output levels and a receiver's input thresholds.

Decision comparison

MOSFET bidirectional level shifter

Check whether an N-channel MOSFET bidirectional level shifter's threshold voltage leaves margin at the lower of two supplies.

Exact ideal relationship

SPI timing-margin analyzer

Calculate simplified full-cycle SPI setup margin from clock period, output delay, flight time, setup requirement, and skew.

Exact ideal relationship

UART baud-rate error

Calculate actual UART baud rate and percentage error from clock frequency, oversampling, and divider register value.

Exact ideal relationship

GPIO current-budget planner

Calculate total GPIO group current and arithmetic margin against a stated group current limit.

Exact ideal relationship

ADC input-scaling network

Calculate the ideal resistive divider ratio and top resistor to map a source voltage range into an ADC input range.

Exact ideal relationship

PWM frequency and resolution planner

Calculate ideal edge-aligned PWM frequency, duty steps, and effective duty resolution from timer clock, prescaler, and counter top.

Exact ideal relationship

Reset RC timing planner

Calculate ideal RC reset-node time constant and the fraction of final value reached at a stated elapsed time.

Exact ideal relationship

Pullup and pulldown resistor designer

Calculate the maximum pull resistor value allowed by worst-case leakage current and a maximum tolerated logic-node voltage rise.