Embedded, Digital, and Interfaces
Model class: Exact relationship
I2C pullup resistor designer
Calculate the feasible I2C pullup-resistance interval from supply voltage, low-level sink limits, bus capacitance, and rise-time limit.
Interactive engine
Start with the stated conditions.
Values stay in this browser. Choose a representative scenario, then calculate deliberately.
Example ready
Calculate to inspect the result.
The result will identify the direct answer, assumptions, and any warning that changes the next decision.
Assumptions to check
- The entered limits are taken from every connected device.
- Bus capacitance includes traces, cables, inputs, and fixtures.
- Existing parallel pullups are combined before selection.
Pullup selection is an interval
An I2C pullup has two opposing limits. It must be low enough to charge bus capacitance inside the rise-time limit, but high enough that a device can pull the line low without exceeding its specified sink current. The intersection is the meaningful answer.
This engine shows both boundaries directly. If they do not overlap, changing a nominal resistor cannot fix the situation. Revisit bus capacitance, mode, topology, voltage, or the actual device limits.
Use total bus conditions
A bench cable, level shifter, connector, multiple boards, and existing pullups can dominate the result. Keep the selected I2C mode and every device data-sheet limit with the calculation, then verify the actual rise time and VOL on the bus.
Verify the interval on the assembled bus
Use the lowest guaranteed sink-current capability among every device that can pull the line low, and use the selected I2C mode’s rise-time requirement. Bus capacitance must include IC pins, traces, cables, connectors, level shifters, test fixtures, and any parallel modules. Existing pullups combine in parallel, so a board-level resistor can be far stronger than the nominal value printed beside it.
If the calculated lower and upper bounds overlap, choose an available value with margin and then measure both the rising edge and low-level voltage at the relevant nodes. If the interval is empty, do not force a compromise resistor and call it compliant. Reduce capacitance, change topology or mode, use a buffer, adjust voltage, or recheck the device limits. Timing, thresholds, noise, and hot-plug behavior remain system checks.
Common mistakes
- Using one device’s sink current for a bus with a weaker device.
- Forgetting parallel pullups.
- Estimating capacitance from IC pins while ignoring wiring and connectors.
Model limit and handoff
Verify all device limits and measure rise time and VOL on the assembled bus.
FAQs
What if the range is empty?
No single resistance satisfies the entered electrical limits. Re-evaluate capacitance, timing mode, sink capability, and topology.