PCB and Transmission Lines
Model class: Standard approximation
PCB thermal-via planner
Estimate ideal parallel thermal conductance of a plated thermal-via array from geometry and copper thermal conductivity.
Interactive engine
Start with the stated conditions.
Values stay in this browser. Choose a representative scenario, then calculate deliberately.
Example ready
Calculate to inspect the result.
The result will identify the direct answer, assumptions, and any warning that changes the next decision.
Assumptions to check
- The entered thermal-via-planner values represent the stated operating condition.
- This standard approximation is evaluated in the declared lumped or first-pass model.
- A thermal-via-planner calculation is not a component qualification or safety approval.
What this thermal-via-planner calculation establishes
Estimate ideal parallel thermal conductance of a plated thermal-via array from geometry and copper thermal conductivity. The useful result is the stated electrical quantity and the decision it supports, not an unstated claim about a finished product. This engine keeps the governing relationship visible so an input, unit, condition, or model boundary can be reviewed before a value becomes a component or layout choice.
Each via's barrel conductance is thermal conductivity times thin-shell barrel cross-section divided by length; total conductance sums the array in ideal parallel. Treat the number as a first-pass result for the declared operating point. When a source, load, temperature, frequency, waveform, component tolerance, or measurement condition changes, repeat the calculation at the relevant corner rather than assuming the nominal answer persists.
Worked decision context
Ten 0.3 mm vias with 25 µm copper plating and 1.6 mm length give about 0.0589 W/K ideal barrel conductance using k = 400 W/mK. That example verifies the equation and illustrates the scale of the result, but it does not select a part by itself. Compare the result with available values, ratings, tolerance bands, and the receiving circuit or physical environment before implementation.
Use the primary output to identify the binding constraint. If it leaves little margin, document which input dominates and use selected-part data, a higher-fidelity model, simulation, or measurement. This is especially important when a small numerical difference changes a thermal, timing, noise, or reliability decision.
Limits and validation handoff
Board spreading resistance, via fill, solder-joint contact resistance, and non-uniform heat distribution all reduce the real effective conductance below this ideal sum. The calculation does not silently include omitted parasitics, installation conditions, manufacturing variation, or product policy. Those conditions can be decisive even when the arithmetic is exact for the selected model.
Record inputs, units, model assumptions, and the intended decision with the result. Verify the leading risk against the selected component data sheet and a representative measurement when the circuit has consequential energy, high voltage, safety, compliance, or reliability requirements.
Common mistakes
- Treating the thermal-via-planner result as a guaranteed operating limit rather than a first-pass standard approximation estimate.
- Mixing a data-sheet value measured under one condition with this thermal-via-planner calculation performed at another.
- Selecting a component before checking the boundary this calculation names: board spreading resistance, via fill, solder-joint contact resistance, and non-uniform heat distribution all reduce the real effective conductance below this ideal sum.
Model limit and handoff
Keep the entered thermal-via-planner conditions with the calculation, then validate the binding limit using the selected component, physical implementation, and representative operating corner.
FAQs
Is this thermal-via-planner result sufficient to approve a design?
No. It applies standard approximation reasoning to the entered thermal-via-planner values and names the checks that still need selected-part data, a higher-fidelity model, or measurement. Board spreading resistance, via fill, solder-joint contact resistance, and non-uniform heat distribution all reduce the real effective conductance below this ideal sum.
What does this thermal-via-planner calculator assume that could make the result wrong?
Each via's barrel conductance is thermal conductivity times thin-shell barrel cross-section divided by length; total conductance sums the array in ideal parallel. If the entered values do not match the real operating condition, the result no longer describes the actual circuit.
Where should this thermal-via-planner result go next?
Compare this thermal-via-planner result with PCB fabrication and standards handoff, then use the stated next decision below the calculator to move from this first-pass number toward an implementation.